------------------------------------------------------------------------------
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--                    Copyright (C) 2017, AdaCore                           --
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------------------------------------------------------------------------------

package body DMA_Interrupt_Handling is

   --------------------------
   -- DMA_Unit_IRQ_Handler --
   --------------------------

   protected body DMA_Unit_IRQ_Handler is

      -----------------
      -- Await_Event --
      -----------------

      entry Await_Event (Occurrence : out DMA_Interrupt) when Event_Occurred is
      begin
         Occurrence := Event_Kind;
         Event_Occurred := False;
      end Await_Event;

      -----------------
      -- IRQ_Handler --
      -----------------

      procedure IRQ_Handler is
      begin
         if Status (Controller.all, Stream, Transfer_Error_Indicated) then
            if Interrupt_Enabled (Controller.all, Stream, Transfer_Error_Interrupt) then
               Disable_Interrupt (Controller.all, Stream, Transfer_Error_Interrupt);
               Clear_Status (Controller.all, Stream, Transfer_Error_Indicated);
               Event_Kind := Transfer_Error_Interrupt;
               Event_Occurred := True;
            end if;
         end if;

         if Status (Controller.all, Stream, FIFO_Error_Indicated) then
            if Interrupt_Enabled (Controller.all, Stream, FIFO_Error_Interrupt) then
               Disable_Interrupt (Controller.all, Stream, FIFO_Error_Interrupt);
               Clear_Status (Controller.all, Stream, FIFO_Error_Indicated);
               Event_Kind := FIFO_Error_Interrupt;
               Event_Occurred := True;
            end if;
         end if;

         if Status (Controller.all, Stream, Direct_Mode_Error_Indicated) then
            if Interrupt_Enabled (Controller.all, Stream, Direct_Mode_Error_Interrupt) then
               Disable_Interrupt (Controller.all, Stream, Direct_Mode_Error_Interrupt);
               Clear_Status (Controller.all, Stream, Direct_Mode_Error_Indicated);
               Event_Kind := Direct_Mode_Error_Interrupt;
               Event_Occurred := True;
            end if;
         end if;

         if Status (Controller.all, Stream, Half_Transfer_Complete_Indicated) then
            if Interrupt_Enabled (Controller.all, Stream, Half_Transfer_Complete_Interrupt) then
               if Double_Buffered (Controller.all, Stream) then
                  Clear_Status (Controller.all, Stream, Half_Transfer_Complete_Indicated);
               else -- not double buffered
                  if not Circular_Mode (Controller.all, Stream) then
                     Disable_Interrupt (Controller.all, Stream, Half_Transfer_Complete_Interrupt);
                  end if;
                  Clear_Status (Controller.all, Stream, Half_Transfer_Complete_Indicated);
               end if;
               Event_Kind := Half_Transfer_Complete_Interrupt;
               Event_Occurred := True;
            end if;
         end if;

         if Status (Controller.all, Stream, Transfer_Complete_Indicated) then
            if Interrupt_Enabled (Controller.all, Stream, Transfer_Complete_Interrupt) then
               if Double_Buffered (Controller.all, Stream) then
                  Clear_Status (Controller.all, Stream, Transfer_Complete_Indicated);
                  --  TODO: handle the difference between M0 and M1 callbacks
               else
                  if not Circular_Mode (Controller.all, Stream) then
                     Disable_Interrupt (Controller.all, Stream, Transfer_Complete_Interrupt);
                  end if;
                  Clear_Status (Controller.all, Stream, Transfer_Complete_Indicated);
               end if;
               Event_Kind := Transfer_Complete_Interrupt;
               Event_Occurred := True;
            end if;
         end if;
      end IRQ_Handler;

   end DMA_Unit_IRQ_Handler;

end DMA_Interrupt_Handling;
